Ongoing demands for more-complex circuits have led to significant achievements that have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often designed as functionally-defined blocks, or physically-defined chips, that operate on a sequence of data and then pass that data on for further processing. This communication from such physically-defined chips can be passed in small or large amounts of data between individual discrete circuits, between integrated circuits (“ICs”), within the same chip, between ICs located on different chips, and between more remotely-located communication circuit arrangements and systems. Regardless of the configuration, the communication typically requires closely-controlled interfaces to insure that data integrity is maintained and that chip-set designs are sensitive to practicable limitations in terms of implementation space and available operating power.
With the increased complexity of circuits, there has been a commensurate demand for increasing the speed at which data is passed between the circuit blocks, and between IC chips. Many of these high-speed communication applications can be implemented using parallel data interconnect transmission in which multiple data bits are simultaneously sent across parallel communication paths. Such “parallel bussing” is a well-accepted approach for achieving data transfers at high data rates.
A typical system might include a number of modules (e.g., one or more cooperatively-functioning chips) that interface to and communicate over a parallel data communication line, for example, a processor chip communicating with a peripheral via a cable, a backplane circuit, an internal bus structure on a chip, an interchip interface, other interconnect, or any combination of such communication media. A sending module transmits data over a bus synchronously with a clock on the sending module. In this manner, the transitions over the parallel signal lines leave the circuits of the sending module in a synchronous relationship with each other and/or to the clock on the sending module. At the other end of the parallel data interconnect, the data is received along with a clock signal; the receive clock is typically derived from or is synchronous with the clock on the sending module. The rate at which the data is passed over the parallel signal lines is sometimes referred to as the (parallel) “bus rate.”
Implementing electronic devices using a plurality of circuit modules, including discrete IC chips, is desirable for a variety of reasons. Accordingly, improving the hardware and associated transmission protocols used to effect data communication over parallel busses permit more practicable and higher-speed parallel bussing applications which, in turn, can directly lead to serving the demands for high-speed circuits while maintaining data integrity. Various aspects of the present invention address the above-mentioned deficiencies and also provide for communication methods and arrangements that are useful for other applications as well.